In a semiconductor device, such as a logic LSI or a memory LSI, basic components, including transistors, diodes, capacitors and resistors, laid out in an electrically isolated manner are first formed on a semiconductor substrate, and then the components are interconnected by wirings.
Such a technique to interconnect elements as described above, i.e., a multilayer interconnection technique, is a crucial technique that dictates the enhancement of LSI performance. As one example of a method for forming multilayer wirings, there is the following method: first, a metal film made of an aluminum (Al) alloy is formed on an insulating film using a sputtering method. Then, a wiring pattern is formed by patterning the metal film by means of photolithography and dry etching. After that, an interlayer insulating film is formed on the wiring pattern using a CVD method and the interlayer insulating film is processed by means of photolithography and dry etching. As the result of this processing, there are formed via holes deep enough to reach the wiring pattern.
In addition, the entire surface of the semiconductor device is covered with tungsten (W) using a CVD method, so as to fill the via holes. After forming such blanket tungsten (hereinafter referred to as blanket W), the blanket W is etched back so that W plugs are buried in the via holes. Then, a wiring pattern is formed on the interlayer insulating film. This wiring pattern is connected to the lower wiring pattern through the W plugs within the via holes. By repeating such a process as described above, it is possible to form desired multilayer interconnections.
Japanese Patent Application Laid-Open No. Hei 02-341 describes a configuration wherein a plated layer, such as a nickel (Ni) layer, a copper (Cu) layer, a tin (Sn) layer or a gold (Au) layer, is coated on the surfaces of Al wirings or titanium nitride (TiN) wirings by means of nonelectrolytic plating when forming the wirings of a semiconductor device, thereby improving wiring reliability.
In addition, Japanese Patent Application Laid-Open No. Hei 03-153030 describes the following method as a method for forming the wirings of a semiconductor device. First, an Au, Ti, TiN or Ti film is formed using a sputtering method and a resist pattern is formed thereon. Next, after forming Au wirings in the openings of the resist pattern by means of electrolytic plating, the resist pattern is separated off and an underlying layer is removed using the Au wirings as a mask.
In recent years, there have often been adopted laminated wirings having a structure wherein cap metal films made of a different metal material are formed on Al alloy films for the purpose of, for example, improving electromigration resistance characteristics. When adopting such wirings having a laminated structure (hereinafter referred to as laminated wirings) as described above, there may arise a problem in a step of forming via holes. This problem arises in the following mechanism: first, an interlayer insulating film covering the wirings is processed by means of dry etching using a fluorine-based gas, to form via holes reaching to the wirings. At this time, there is a case that a foreign substance (reaction product) remains on the sidewalls of the via holes at the time of overetching the via holes, depending on a material composing the cap metal films of laminated wirings. This foreign substance cannot be removed in a step of resist separation (dry ashing and wet treatment). As a result, such a problem as contact failure occurs, thereby possibly degrading the yield of multilayer interconnections.
As described above, the related art has had the problem that it is not possible to form reliable multilayer interconnections since a problem can easily occur when forming via holes in a case where the wirings of a laminated structure are used.